View CY7C1049CV33-8ZSXC_966540.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY7C1049CV33
4-Mbit (512 K x 8) Static RAM
4-Mbit (512 K x 8) Static RAM
Features
Functional Description
The CY7C1049CV33 is a high performance Complementary metal oxide semiconductor (CMOS) Static RAM organized as 524,288 words by eight bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049CV33 is available in standard 44-pin TSOP II package with center power and ground (revolutionary) pinout.
Temperature ranges Commercial: 0 C to 70 C Industrial: -40 C to 85 C High speed tAA = 8 ns Low active power 360 mW (max) 2.0 V data retention Automatic power down when deselected Transistor- transistor logic (TTL) compatible inputs and outputs Easy memory expansion with CE and OE features

Logic Block Diagram
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE WE OE
INPUT BUFFER ROW DECODER
IO0 IO1 SENSE AMPS IO2 IO3 IO4 IO5 IO6
512K x 8 ARRAY
COLUMN DECODER
POWER DOWN
IO7
A13 A14
A15
A16
A17
Cypress Semiconductor Corporation Document #: 38-05006 Rev. *M
*
198 Champion Court
A18
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 14, 2011
[+] Feedback
CY7C1049CV33
Contents
Selection Guide ................................................................ 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 AC Test Loads and Waveforms ....................................... 5 AC Switching Characteristics ......................................... 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13
Document #: 38-05006 Rev. *M
Page 2 of 13
[+] Feedback
CY7C1049CV33
Selection Guide
Description Maximum access time Maximum operating current Maximum CMOS standby current -8 8 100 10 -10 10 100 10 Unit ns mA mA
Pin Configuration
Figure 1. 44-pin TSOP II (Top View)
NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
NC NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC
Pin Definitions
Pin Name A0-A18 I/O0-I/O7 NC[1] WE CE OE 44-pin TSOP II Pin Number 3-7, 16-20, 26-30, 38-41 9, 10, 13, 14, 31, 32, 35, 36 1, 2, 21, 22, 23, 24, 25, 42, 43, 44 15 8 37 I/O Type Input Input/Output No connect Input/Control Input/Control Input/Control Description Address inputs used to select one of the address locations. Bidirectional data I/O lines. Used as input or output lines depending on operation. No connects. This pin is not connected to the die. Write Enable input, active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted. Chip Enable input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. Ground for the device. Should be connected to ground of the system. Power supply inputs to the device.
VSS, GND VCC
12, 34 11, 33
Ground Power supply
Note 1. NC pins are not connected on the die.
Document #: 38-05006 Rev. *M
Page 3 of 13
[+] Feedback
CY7C1049CV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ -65 C to +150 C Ambient temperature with power applied .......................................... -55 C to +125 C Supply voltage on VCC to Relative GND[2] ................................-0.5 V to +4.6 V
DC voltage applied to outputs in High Z State[2] ................................. -0.5 V to VCC + 0.5 V Input Voltage[2] ................................... -0.5 V to VCC + 0.5 V Current into Outputs (LOW) ........................................ 20 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0 C to +70 C -40 C to +85 C VCC 3.3 V 0.3 V 3.3 V 0.3 V
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX ICC ISB1 Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage[2] Input load current VCC operating supply current Automatic CE power down current --TTL inputs Automatic CE power down current --CMOS Inputs GND < VI < VC VCC = Max, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3 V, VIN > VCC - 0.3 V, or VIN < 0.3 V, f=0 Test Conditions VCC = Min; IOH = -4.0 mA VCC = Min; IOL = 8.0 mA -8 Min 2.4 - 2.0 -0.3 -1 - - Max - 0.4 VCC + 0.3 0.8 +1 100 40 Min 2.4 - 2.0 -0.3 -1 - - -10 Max - 0.4 VCC + 0.3 0.8 +1 100 40 Unit V V V V A mA mA
ISB2
-
10
-
10
mA
Capacitance
Parameter[3] CIN COUT Description Input capacitance I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max 8 8 Unit pF pF
Thermal Resistance
Parameter[3] Description Thermal resistance (Junction to ambient) Thermal resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 44-pin TSOP-II Unit 41.66 10.56 C/W C/W
JA JC
Notes 2. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 on page 5 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 2 on page 5 (c). 3. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05006 Rev. *M
Page 4 of 13
[+] Feedback
CY7C1049CV33
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
8, 10-ns devices: OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5 V Z = 50
30 pF*
(a)
High Z characteristics: 3.0 V 90% GND 10% ALL INPUT PULSES 90% 10% 3.3 V OUTPUT 5 pF R2 351 R 317
Rise Time: 1 V/ns
(b)
Fall Time: 1 V/ns
(c)
Note 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 2 (c).
Document #: 38-05006 Rev. *M
Page 5 of 13
[+] Feedback
CY7C1049CV33
AC Switching Characteristics
Over the Operating Range Parameter [5] Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the first access Read cycle time Address to data valid Data Hold from Address Change CE LOW to data valid OE LOW to data valid OE LOW to Low Z[7] Z[7, 8] Z[7, 8] OE HIGH to High CE HIGH to High 100 8 - 3 - - 0 - 3 - 0 - 8 6 6 0 0 6 4 0 3 - - - 8 - 8 5 - 4 - 4 - 8 - - - - - - - - - 4 100 10 - 3 - - 0 - 3 - 0 - 10 7 7 0 0 7 5 0 3 - - - 10 - 10 5 - 5 - 5 - 10 - - - - - - - - - 5 s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description -8 Min Max Min -10 Max Unit
CE LOW to Low Z[7] CE LOW to power up CE HIGH to power down Write cycle time CE LOW to write end Address setup to write end Address hold from write end Address setup to write start WE pulse width Data setup to write end Data hold from write end WE HIGH to Low WE LOW to High Z[7] Z[7, 8]
Write Cycle [9, 10]
Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 6. tPOWER gives the minimum amount of time that the power supply should be at stable, typical VCC values until the first memory access can be performed. 7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of Figure 2 on page 5. Transition is measured 500 mV from steady-state voltage. 9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05006 Rev. *M
Page 6 of 13
[+] Feedback
CY7C1049CV33
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled) [11, 12]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 4. Read Cycle No. 2 (OE Controlled) [12, 13] 2
ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE DATA OUT tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycles. 13. Address valid before or similar to CE transition LOW.
Document #: 38-05006 Rev. *M
Page 7 of 13
[+] Feedback
CY7C1049CV33
Switching Waveforms (continued)
Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [14, 15]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA I/O NOTE 16 tHZOE DATA VALID tHD
Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW) [15]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O NOTE 16 tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
Notes 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 16. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 38-05006 Rev. *M
Page 8 of 13
[+] Feedback
CY7C1049CV33
Truth Table
CE H L L L OE X L X H WE X H L H I/O0-I/O7 High Z Data Out Data In High Z Power Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 8 10 Ordering Code CY7C1049CV33-8ZSXC CY7C1049CV33-10ZXI Package Diagram Package Type Operating Range Commercial Industrial
51-85087 44-pin TSOP II (Pb-free) 51-85087 44-pin TSOP II (Pb-free)
Ordering Code Definitions
CY 7C 1 04 9 C V33 - XX ZS X X Temperature Range: X = C or I C = Commercial; I = Industrial X = Pb-free; X Absent = Leaded Package Type: ZS = 44-pin TSOP II Speed Grade: XX = 8 ns or 10 ns V33 = 3.0 V to 3.6 V Process Technology: C 150 nm Data width: x 8-bits 4-Mbit density Fast Asynchronous SRAM Marketing Code: 7C = SRAMs Company ID: CY = Cypress
Document #: 38-05006 Rev. *M
Page 9 of 13
[+] Feedback
CY7C1049CV33
Package Diagram
Figure 7. 44-pin TSOP Z44-II, 51-85087
51-85087 *C
Document #: 38-05006 Rev. *M
Page 10 of 13
[+] Feedback
CY7C1049CV33
Acronyms
Acronym CE CMOS I/O OE RAM SRAM TSOP TTL WE chip enable complementary metal oxide semiconductor input/output output enable random access memory static random access memory thin small outline package transistor-transistor logic write enable Description
Document Conventions
Units of Measure
Symbol C MHz A s mA mm ms mW ns % pF V W degree Celsius Mega Hertz micro Amperes micro seconds milli Amperes milli meter milli seconds milli Watts nano seconds ohms percent pico Farad Volts Watts Unit of Measure
Document #: 38-05006 Rev. *M
Page 11 of 13
[+] Feedback
CY7C1049CV33
Document History Page
Document Title: CY7C1049CV33, 4-Mbit (512 K x 8) Static RAM Document Number: 38-05006 Rev. ** *A *B *C *D *E ECN 112569 114091 116479 262949 300091 344595 Orig. of Change HGK DFP CEA RKF RKF SYT Submission Date 03/06/02 04/25/02 09/16/02 See ECN See ECN See ECN New data sheet Changed Tpower unit from ns to s Add applications foot note to data sheet, page 1. Added Automotive-E Specs Added JA and JC values on Page #3. Added -20-ns Speed bin Added Pb-free package on page #8 Removed shading for CY7C1049CV33-15ZSXE in the ordering Information on page 9 Added Automotive-A information Removed 8 ns and 20 ns speed bins, Changed tPOWER spec from 1 s to 100 s, Updated Ordering Information table. Removed inactive parts from the ordering information table. Updated package diagrams. Description of Change
*F
2615344
VKN/PYRS
12/03/08
*G *H *I *J *K
2841563 2898958 2954734 3072834 3185812
NXR/ AJU AJU PRAS PRAS
01/07/2010 Added CY7C1049CV33-10VXA to Ordering Info table. 03/25/10
06/30/2010 New Part Number added CY7C1049CV33-10ZXC to Ordering Info table. 11/12/2010 Removed obsolete parts and updated package diagram. 03/02/2011 Updated Features. Updated Functional Description. Updated Selection Guide (Added 8 ns speed grade devices and removed 10 ns, 12 ns, and 15 ns speed grade devices). Removed Figure 36-pin SOJ (Top View) in Pin Configuration. Updated Electrical Characteristics (Added 8 ns speed grade devices and removed 10 ns, 12 ns, and 15 ns speed grade devices). Deleted 36-pin SOJ column in Thermal Resistance. Updated AC Switching Characteristics (Added 8 ns speed grade devices and removed 10 ns, 12 ns, and 15 ns speed grade devices). Added Units of Measure. Dislodged Automotive information to 001-67511. Removed SOJ package related information in all instances in the document. 05/25/11 Updated Functional Description (Removed "For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines."). Updated Selection Guide (Added 10 ns speed grade devices). Updated Electrical Characteristics (Added 10 ns speed grade devices). Updated Note 2 in page 4 as "AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 on page 5 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 2 on page 5 (c)". Updated Figure 2. Updated Note 4 in page 5 as "AC characteristics (except High Z) are tested using the load conditions shown in Figure 2 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 2 (c)". Updated AC Switching Characteristics (Added 10 ns speed grade devices). Updated Ordering Information (Included CY7C1049CV33-10ZXI).
*L
3250938
PRAS
*M
3282230
AJU
06/14/2011 Updated in new template.
Document #: 38-05006 Rev. *M
Page 12 of 13
[+] Feedback
CY7C1049CV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-05006 Rev. *M
Revised June 14, 2011
Page 13 of 13
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback

▲Up To Search▲

Price & Availability of CY7C1049CV33-8ZSXC

	To Download CY7C1049CV33-8ZSXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .